ADC APROXIMACIONES SUCESIVAS PDF

ADC APROXIMACIONES SUCESIVAS PDF

Para la descripción hardware del comportamiento del algoritmo de entrenamiento adaptativo por aproximaciones sucesivas, se estudió la arquitectura de los. “Convertidores ADC y DAC”. Objetivos. digital (ADC) y el digital analógico ( DAC).. Material y funcionamiento de aproximaciones sucesivas. El tiempo de. Análisis, modelado y diseño de Convertidores. Analógicos-Digitales de Aproximaciones. Sucesivas (SAR-ADCs) con Redundancia. Digital.

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The basic functions of analogue-to-digital conversions are: Signal protection from interference voltage level increase ; Good signal transfer due to high impedance inputs and low impedance output; Improvement to signal precision by adjustment of the voltage level at the ADC input.

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There are different types of op-amps: Flexible feedback networking; Flexible modes optimized current consumption and performance; User configurable as: An OA consists of: Inverting input, V 1; Non inverting input, V 2. Single output, V 0: Open-loop differential gain ideally: High input impedance, Z IN ideally: Output voltage is displaced from 0 V ideally: Resistor R f is connected from the output V 0 back to the inverting input, to control the gain of the OA with negative feedback; V IN applied to the inverting input; Gain of the inverting OA: The single supply circuitry shown is only applicable for negative input voltages, and input signal is loaded by R 1.

Resistor R f is connected from the output V 0 back to the inverting input to control the gain of the OA with negative feedback; V IN applied to the non inverting input; Gain of the non-inverting OA: Unity gain buffer voltage follower topology: Output in phase with the input; Buffer isolation between the circuit and the charge ; Power amplifier; Impedance transformer; Input impedance: Inverting and non-inverting topologies combined; Output signal is the amplification of the difference between the two input signals: Three OpAmp Differential topology: Internal routing of the OA signals: Configuration of control registers: Ideal operational amplifiers have: Quiz The digital code can be displayed, processed, stored or transmitted.

Is more or less defined by bandwidth range; Require an established resolution range. Degree of conformity of a digital code representing the analogue voltage to its actual true value; Can express as the degree of truth.

Depends on the following specifications: Speed; Accuracy, also depends on the circuitry type: Determines how far an output code is from a neighbouring output code. Is the integral of the DNL errors; Represents the difference between the measured converter result and the ideal transfer-function value. No DNL error requires that: In bipolar systems, the offset error shifts the transfer function but does not reduce the number of available codes.

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Full-scale error aec the offset error, measured at the last ADC transition on the transfer-function curve and compared with the ideal ADC transfer function; May or not include errors in the voltage reference of the ADC. Shift the analogue input x and digital output y axes of the transfer function so that the negative full-scale point aligns with the zero point: The conversion result represents the bipolar zero offset error.

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Perform a gain adjustment.

Previous methodology is applicable if the offset is positive; Gain error can be corrected by software considering a linear function in terms of the ideal transfer function slope m 1 and measured m 2: Harmonics occur at multiples of the input frequency: Voltage Reference internal or external: Besides the settling time, the source of the reference voltage errors is related to the following specifications: Affects the performance of an ADC converter based on resolution; Voltage noise: Specified as either an RMS value or a peak-topeak value; Load regulation: Current drawn by other components will affect the voltage reference; Temperature effects offset drift and gain drift.

Signal-to-noise ratio without distortion components; Determines where the average noise floor of the converter is, setting an ADC performance limit for noise. For an n bit ADC sine wave input is given by: Lowers the average noise floor of the ADC; Spreads the noise over more frequencies equalise total noise. Oversampling an ADC is a common principle to increase resolution; It reduces the noise at any one frequency point. Spurious-free dynamic range SFDR: Defined as the ratio of the RMS value of an input sine wave to the RMS value of the largest trace observed in the frequency domain using a FFT plot; If the distortion component is much larger than the signal of interest, the ADC will not convert small input signals, thus limiting its dynamic range.

MSPF ezf and Experimenter s board.

Conversores Digital-analógicos (DAC) Conversores ADC y DAC

The performance of an ADC is expressed by which specifications: A low cost, low power consuming application that requires a 12 bit resolution with a Hz output data rate should use an ADC with the architecture: Data loggers; Temperature sensors; Bridge sensors resistive e.

Determines the digital word by approximating the analogue input signal using an iterative process, as follows: Discharge the capacitor array to the comparator s V offset; Sample the input aproximacones V S and hold; Switch aproximacionrs of the capacitors in the array to V S; Switch the capacitors to charge the comparator’s input; Initiate a binary search: Converts an analogue input to its bit digital representation; Stores the result in the ADC10MEM register; The analogue conversion range is limited by the upper and lower limits: One conversion in multiple channels, beginning with the channel selected by INCHx bits and decrementing to channel A0, looping through a specified number of ADC10MEM registers and stopping after the conversion of channel A.

Repeated conversions for multiple channels, beginning with the channel selected by INCHx bits and decrementing to channel Aadc. The sequence ends after conversion of channel A0, and the next aproximaicones signal re-starts the sequence.

The results in the least significant 10 bits. The results in the most significant 10 bits. It sucesibas only the 15 most significant bits. Bit 0 is always read as. Conversion modes; Integrated temperature sensor. ADC12 timer trigger for reference settling: Non-sequential conversion single- or repeat-singlechannel: Sequential conversion sequence-of- or repeat-sequenceof-channels: ADC12TOV is set when another sample-and-conversion is requested before the current conversion is completed.

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The DMA is triggered after the conversion in single channel modes or after the completion of sequence of channel modes. These bits are configured as the previous ones SHT1x. Refer to the ADC10 to see their description.

Bits are always 0.

The results are stored in the least significant 12 bits. Two laboratories have been developed to make use of the SAR ADCs included in the different hardware development tools: Like the previous laboratory exercise Lab4this one is also composed of sub-tasks. This laboratory has been developed for the Code Composer Essentials version 3 software development tool only. The voltage value is converted into temperature using the mathematical formula provided in the ADC10 sub-section; After transferring the value to the flash memory, the system returns to low power mode LPM3.

The resources used by the application are: The application starts by stopping the Watchdog Timer; System tests for calibration constants stored in info memory segment A.

While variable min is lower than 60, the temperature is written to flash memory. Configure the ADC10 sample-and-hold time: What is the value to write to the configuration register?

Configure the following registers: Monitor the temperature variation during 1 hour: Monitor the temperature variation over 1 hour: The data starts at address 0x with a length of 3C; Run the application and let the temperature data logger acquire values for 1 hour; Use a heater or a fan to force temperature variations during the measurement period; When execution reaches the breakpoint, the file will be available in your file system; Construct a graph to plot the temperature variation obtained by the data logger Lab5A: The resources used by the application following the signal modification steps are: The laboratory is organized as follows: The ADC12 module is configured in order to have the following characteristics: The ADC12 module operates with reference voltages: The channel selected to perform the analogue-to-digital conversion is channel A1.

This channel is internally connected to the output of OA0. Inverting input is connected to the DAC12 channel 0; The amplifier gain is configured as unity; The input is configured in rail-to-rail mode; The output is connected to channel A1. This laboratory uses the previous modules to construct an analogue signal chain. The input voltage V in is in the range 0 V and 2. With the aid of a voltmeter, measure the analogue input voltage A6 DAC12 channel 0 output.

The value should be in the region of 0. The voltage value should be the same. Verify the conversion result of the ADC Verify the voltage at A0.

It should be the double of the input voltage A1 output of the OA0 shown in step 2; Execute the code. Do not exceed the V o maximum value 2.